VLSI Design Services and Custom IP Solutions
ASIC Physical Design and Verification Services
VLSI Design Services and Custom IP Solutions
ASIC Physical Design and Verification Services
About JunexIC Company
Our Vision
At JunexIC we (Jatan Shah and Irene Liu) strive to create and deploy VLSI integrated Circuit design flows at our customer sites with the primary goal of achieving rapid time to market and meet the production quality requirements for large volume production
For more details you can reach to us jshah@junexic.com
Our Services
Overview
25+ years of experience in IC physical design/implementation services
Low power IC design
- UPF/CPF development
- CLP based verification
DFT insertion (scan, Mbist), DFT verification
Basic Stuck-At , At-speed scan insertion, Compression , Mbist, Boundary scan
Timing Constraint (SDC) development for small to medium (~ 3 million instance) SOC designs
Custom IPs designed for connectivity products
- SPI / I2C design and implementation
- Custom IP development and silicon implementation under NDA for tunable Wifi devices (example: Kyocera-AVX EC477 , EC624 chip full digital design and implementation. Spec to GDS) . Implemented a proprietary single wire communication link with no phase locking at receieve
Exceptional Customer Service
We pride ourselves on providing exceptional customer service to all our clients. Our team is always ready to answer your questions, provide advice, and offer support whenever you need it.
VLSI Capabilities
IC Physical Design Services. : Synthesis/Place and Route / Physical verification / Conformal LEC /
Foundry Process Node Experience
Older nodes (TSMC: 90nm,65nm, 55lp, 45g), TSMC CLN22LP (CRN28HPCPLUS) , TSMC CLN12FFCPLUS (16FFCPLUS), TSMC N5, GF-IBM 9HP SiGe, Tower Jazz SBC18, GF013, GF22FDX, GF-IBM 45RFSOI
IC Chip Implementation
Flow development and deployment
Server Colocation support for VLSI workflows
Server selection/ EDA License optimization
Custom IP implementation for mixed-signal devices, Serial IP (SPI,I2C) Spec to GDS implementation
DFT
- Stuck at and At-speed scan insertion
- Mbist : At-speed and slow mbist. JTAG - TDR insertion and build of IJTAG networks
- Scan compression block insertion
IR Analysis
- Power / IR Analysis : Static , Dynamic (vector based)
Synopsys library generation for IPs from characterization data
Signoff setup (MMMC) based on foundry or customer requirements
Design Verification
RTL and Gate verification of Custom IPs designed. Serial and other Custom IPs.
DFT verification
Toolsets
Cadence Implementation Tools
- Genus
- Innovus
- Tempus
- Voltus
Cadence Conformal
LEC, CLP
Cadence Pegasus Physical Verification Tools
LVS,DRC, Other checks
Siemens Tessent toolset
Siemens Calibre Toolset
Calibre, CalibreDRV