VLSI Design Services and Custom IP Solutions
ASIC Physical Design and Verification Services
VLSI Design Services and Custom IP Solutions
ASIC Physical Design and Verification Services
Our Services
About JunexIC Company
Our Vision
JuenxIC specializes in creating and deploying VLSI silicon implementation flows at customer sites as well as providing turnkey solutions for IC implementation (synthesis, DFT, PNR, STA Signoff) using Cadence Genus,Innovus,Tempus,Voltus EDA tools
For more details email: jshah@junexic.com
Overview
25+ years of experience in IC physical design/implementation services
Low power IC Implementation
- Multi-domain Multi-Switch IC Physical design: Floorplanning (Multi-domain), CTS, all PNR, Signoff
- UPF/CPF development support
- CLP based verification support
DFT insertion (Scan, MBIST), DFT verification
Stuck-At, At-speed scan insertion, Compression, Mbist, Boundary scan using Cadence Modus toolsuite or Siemens Tessent toolset
Timing Constraint (SDC) development support for small to medium (~ 3 million instance) SOC designs
Custom IPs designed for connectivity products
- SPI / I2C design and implementation : Custom SPI IPs (Spec to GDS). Silicon proven. Focus on mixed signal RF products. Mixed Signal nodes supported : GF 9HP SiGe , GF 45 SPCLO, TSMC 12FF
- Custom IP development and silicon implementation under NDA (Spec to GDS). With focus on low power (IOT products)
- Custom communication IPs (Spec to Silicon)
VLSI
IC Physical Design Services: Synthesis/Place and Route / Physical verification / Conformal LEC /
Foundry Process Node Experience
Older nodes (TSMC: 90nm,65nm, 55lp, 45g), TSMC CLN22LP, CRN28HPCPLUS,CLN12FFCPLUS 16FFCPLUS, TSMC N7,N5, GF-IBM 9HP SiGe, Tower Jazz SBC18, GF013, GF22FDX, GF-IBM 45RFSOI, 45SPCLO
IC Chip Implementation
IC Physical Design Flow development and deployment. Starting from Synthesis, PNR and Phsycial verification
Custom IP implementation for mixed-signal devices, Serial IP (SPI,I2C) Spec to GDS implementation
DFT
- Stuck at and At-speed scan insertion
- Mbist: At-speed and slow mbist. JTAG - TDR insertion and build of IJTAG networks
- Scan compression block insertion
Formal Verification
- Conformal LEC/ CLP
IR Analysis
- Power / IR Analysis: Static , Dynamic (vector based)
Synopsys library generation for IPs from characterization data
Signoff setup (MMMC) based on foundry or customer requirements
Design Verification
RTL and Gate verification of Custom IPs designed. Serial and other Custom IPs.
DFT RTL and Gate Level Verification
Toolsets
Cadence Implementation Tools
- Genus
- Innovus
- Tempus
- Voltus
Cadence Conformal
LEC, CLP
Cadence Pegasus Physical Verification Tools
LVS, DRC, Other checks
Siemens Tessent toolset
Siemens Calibre Toolset
Calibre, CalibreDRV